Transmitting certain types of data can involve transforming the data from a parallel state into a serial state for transmission. Once the data is transmitted in its serial state, it can be de-serialized into it former parallel state. For example, assume that 10 bits (in a parallel state) at 200 MHz are desired to be transmitted from a transmitter to a receiver. To effectuate transmission, the 10 bits can be converted (i.e. serialized) to individual bits and transmitted at 2.5 Gbit/second. At the receiving end, the transmitted bit stream can be converted back into its parallel state by a de-serializer that provides the data as 10 bits at 200 MHz.
The process of serializing and de-serializing data necessarily brings into play the clock domains associated with both the input data and the serializer/de-serializer. Consider, for example, FIG. 1, which shows a typical transmit parallel interface 100. On a so-called user side, parallel data 102 resides in an environment associated with a first clock domain, say clock domain A. On the serializer/de-serializer side, the data resides in an environment associated with a second clock domain, say clock domain B. Since the clocks in the two domains can be from different clock sources, the timing relationship of the two can be arbitrary. Parallel data 102 is typically received by a circuit element, such as one or more flip flops 104 that are clocked in domain B, and then provided to a serializer 106 for serialization and then subsequent transmission.
An important problem associated with the transmit parallel interface 100 pertains to how to safely transmit the data from one clock domain to another clock domain. Specifically, timing synchronization for the transmit parallel interface of high speed I/O is needed to avoid any setup time or hold time violation for the input data of the transmit parallel interface. One way of doing this is to ensure that the setup and hold window for the data is sufficient. The setup and hold time constraint requires data to be valid for certain amount of time relative to a time reference. Otherwise, the data cannot be received correctly. The implementation can affect system clocking complexity and data latency, as is known.
For example, in the past, attempts to align the clocks on both sides of the interface have been made, but have been found to be inadequate. Specifically, some implementations attempt to align the clocks on both sides of the interface by using feedback circuitry such as phase-locked loops. This solution adds clocking complexity that can be undesirable in many instances. Other implementations have attempted to use FIFO or flip flop pairs. These implementations, however, increase data latency as well as the design complexities in generating the pointer select.
Accordingly, this invention arose out of concerns associated with providing improved timing synchronization methods and systems for use with transmit parallel interfaces, that reduce clocking complexities and mitigate data latency concerns.